Re: [myhdl-list] delta cycles

[Ben <ben...@gm...>]

On Thu, Apr 19, 2012 at 09:10, Thomas Heller <th...@ct...> wrote:
> Please consider a standard counter, something like this:
>
> def Counter(clock, count):
>     @always(clock.posedge)
>     def logic():
>         count.next = count + 1
>     return logic
>
> When this counter is simulated, count changes a delta cycle after
> the positive clock edge.  When traceSignals is used to write a VCD file,
> gtkwave shows that the count changes exactly at the same time as the
> clock edge.  This is confusing (at least in more complicated cases) in
> the timing diagram.
>

The solution I found that suited the most my need for this feature was
to alter the following line:

http://hg.myhdl.org/cgi-bin/hgwebdir.cgi/myhdl/file/7a860a7fb408/myhdl/_Signal.py#l86

And change the default value of delay from None to 1

The reasoning behind that is that is that you almost never want this
setting to be set per Signal, you want it project-wide or you're gonna
be stucked in inconsistency loops ... This has for unique consequence
to make the VCD easier to debug. The generated code will look exactly
the same.

The drawback of this method is that you have to set the duration of
your clock(s) accordingly so that your system be stable before the
next clock rises.

Regards,
Benoît.

> Of course, MyHDL allows to simulate a propagation delay for the count
> signal by specifying a delay parameter in the creation of the count
> signal:
>
> count = Signal(intbv(0)[16:], delay=1)
>
> Typically, the signal instantiation takes place in the testbench, not
> in the instance.  I would like to define the prop-delay in the instance;
> I found two ways of doing that.
>
> First:
>
> def Counter(clock, count):
>     @instance
>     def logic():
>         while 1:
>             yield clock.posedge
>             yield delay(1)
>             count.next = count + 1
>     return logic
>
> Second (with an appropriate definition of the clone_signal() function):
>
> def Counter(clock, count):
>     count_internal = clone_signal(count, delay=1)
>     @always(clock.posedge)
>     def logic():
>         count_internal.next = count_internal + 1
>     @always_comb
>     def output():
>         count.next = count_internal
>     return logic, output
>
> I guess (haven't tried) the first one would create non-synthesizable
> VHDL, but the second one should.
>
>
> Thomas
>
>
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