[myhdl-list] delta cycles

[Thomas H. <th...@ct...>]

Please consider a standard counter, something like this:

def Counter(clock, count):
     @always(clock.posedge)
     def logic():
         count.next = count + 1
     return logic

When this counter is simulated, count changes a delta cycle after
the positive clock edge.  When traceSignals is used to write a VCD file,
gtkwave shows that the count changes exactly at the same time as the
clock edge.  This is confusing (at least in more complicated cases) in
the timing diagram.

Of course, MyHDL allows to simulate a propagation delay for the count
signal by specifying a delay parameter in the creation of the count
signal:

count = Signal(intbv(0)[16:], delay=1)

Typically, the signal instantiation takes place in the testbench, not
in the instance.  I would like to define the prop-delay in the instance;
I found two ways of doing that.

First:

def Counter(clock, count):
     @instance
     def logic():
         while 1:
             yield clock.posedge
             yield delay(1)
             count.next = count + 1
     return logic

Second (with an appropriate definition of the clone_signal() function):

def Counter(clock, count):
     count_internal = clone_signal(count, delay=1)
     @always(clock.posedge)
     def logic():
         count_internal.next = count_internal + 1
     @always_comb
     def output():
         count.next = count_internal
     return logic, output

I guess (haven't tried) the first one would create non-synthesizable
VHDL, but the second one should.


Thomas