Re: [myhdl-list] initial blocks in Verilog

[John S. <jo...@sa...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

> 
> Thanks for the post John,
> 
> Not sure if you simply wanted to share some changes that you have made 
> or if you want to provide a patch for a future release.  If the later is 
> the case you will want to review the following,
> 
> http://www.myhdl.org/doku.php/dev:patches
> 
> For this task is sounds like you tested the main open item, Quartus 
> support of initialized values.  To address close this issue the 
> following would need to be completed:
> 
>    * VHDL initial value and Verilog.
>    * testing other synthesis (others probably can assist).
>    * test cases to include in the unit testing.
> 
> Regards,
> Chris

At the moment I just want to share the patch. I'm not sure if it really covers
off all the issues regarding initial blocks, even just for Verilog. I'm
certainly not competent to do any of the VHDL-related stuff, having only really
just started with Verilog. I could perhaps pursue a proper resolution with some
help, but I won't be able to start that until June or July at the earliest.

regards,
John