Re: [myhdl-list] Describing a rom for Altera Quartus

[Norbo <Nor...@gm...>]

Just to share my insights on this topic:
I actually have never seen a altera FPGA with have dedicated ROM Blocks
inside.
Altera FPGAs are usually built out of LUT4 Blocks, some Registers, and
some dedicated memory or RAM Blocks (they need a positive clockege to
output data).
So am not quite sure what this (attribute romstyle : string;  attribute
romstyle of q : signal is "M9K";) does?

So my understanding on how quartus normaly maps is:

    * Rom with asynchron output
	-->  This is put on the FPGA into LUT4 Blocks
	     (this shows up as normal logic (combinatorical functions) synthesis
report)
    * Rom with sycnhron output (output is valid after the positive clk edge)
	--> This is put on the FPGA into the dedicated memory or RAM Blocks
(where the write logic is not used and they are pre
                initialized by the rom content)
    * RAM with asynchron output
	--> This is put on the FPGA into LUT4 Blocks and registers (because the
memory blocks need the clkedge for the output)
    * RAM with synchron output
           --> This is put on the FPGA into the dedicated memory or RAM
Blocks

And my understanding on how to write this down in myhdl so that quartus/
inferece the appropriate logic:

    * Rom with asynchron output:
       (example from the manual)
       ----------------------------------------
       from myhdl import *
       def rom(dout, addr, CONTENT):

	@always_comb
	def read():
	    dout.next = CONTENT[int(addr)]

	return read
       ----------------------------------------


    * Rom with sycnhron output: (output is valid after the positive clk  
edge)
       ----------------------------------------
       from myhdl import *
       def rom(clk,dout, addr, CONTENT):

	@always(clk.posedge)
	def read():
	    dout.next = CONTENT[int(addr)]

	return read
       ----------------------------------------


    * RAM with asynchron output_ (without initialisation of the memory)
       (example from the manual)
       ----------------------------------------
       from myhdl import *
       def RAM(dout, din, addr, we, clk, depth=128):
	""" Ram model """
	mem = [Signal(intbv(0)[8:]) for i in range(depth)]
	
	@always(clk.posedge)
	def write():
	    if we:
		mem[addr].next = din
	
	@always_comb
	def read():
	    dout.next = mem[addr]
	
	return write, read
        ----------------------------------------

    * RAM with synchron output (without initialisation of the memory):
       ----------------------------------------
       from myhdl import *
       def RAM(dout, din, addr, we, clk, depth=128):
	""" Ram model """
	mem = [Signal(intbv(0)[8:]) for i in range(depth)]
	
	@always(clk.posedge)
	def write_read():
	    if we:
		mem[addr].next = din
	    dout.next = mem[addr]
	
	return write_read
        ----------------------------------------

    * RAM with asynchron output (with pre-initialisation of the memory
content):
        Dont know a way to describe this in myhdl (i think the list of  
signal
would need to be initializable) then it could work.
       	
    * RAM with synchron output (with pre-initialisation of the memory
content):
        Dont know a way to describe this in myhdl


greetings
norbo


Am 28.03.2012, 10:56 Uhr, schrieb Frederik T. <sp...@ne...>:

> Hello Chris,
>
> I just tried it without success. Without the extra attributes the rom
> was made off logic elements. After I added them to the VHDL code
> everything was okay.
>
> Do you have another idea?
>
>
> Regards,
>
> Frederik
>
> Am 27.03.2012 20:32, schrieb Christopher Felton:
>> On 3/27/2012 11:18 AM, Frederik T. wrote:
>>> This is the template I found in Quartus II to describe a single port  
>>> rom:
>> <snip>
>>> begin
>>>
>>> 	process(clk)
>>> 	begin
>>> 	if(rising_edge(clk)) then
>>> 		q<= rom(addr);
>>> 	end if;
>>> 	end process;
>>>
>>> end rtl;
>>>
>>> It looks different then the case-when statements.
>>> Maybe I should generate VHDL code based on this template.
>>>
>>>
>>> Regards,
>>>
>>> Frederik
>>>
>>
>> I haven't tested/tried.  You should be able to use the "clocked"
>> generator in your MyHDL code for the read port and get similar generated
>> VHDL that Quartus should recognize as a ROM.  Instead of the always_comb
>> in the read port use a always(clk.posedge).
>>
>> Hope that helps,
>> Chris
>>
>>
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