[myhdl-list] Memory hungry and slow ram

[Frederik T. <sp...@ne...>]

Hello all,

I made a synchronous dual port ram with a single write port.

def dual_port_ram(clk, addr_a, addr_b, we_a, data_a, q_a, q_b,
datawidth, addrwidth):
    '''
        clk -- clock
        addr_a, addr_b -- addresses a, b
        data_a -- input data
        we_a -- write enable
        q_a, q_b -- output a, b
        datawidth -- width of data
        addrwidth -- bitwidth of addr

        A dual port ram with a single write port
    '''

    LMAX = 2**(datawidth-1)

    ram = [Signal(intbv(0, max=LMAX, min=-LMAX)) for i in
range(2**addrwidth)]

    @always(clk.posedge)
    def ports():
        if we_a:
            ram[addr_a].next = data_a

        q_a.next = ram[addr_a]
        q_b.next = ram[addr_b]

    return ports

It works in Xilinx ISE and Altera Quartus without any problems.

I realized that this design becomes really slow, if addrwidth rises.
This ram is used in a bit reverser component for an FFT processor. This
FFT than needs 3N Signals to hold all the data needed, where N is the
number of FFT points.

I tried to simulate an FFT with N=65536 it was really slow and took
about 30 minutes on a modern machine. The simulation lasts three FFT
frames. So simulation N samples takes about 10 minutes.

After that I tried to simulate the next FFT size N=131072 and I had to
abort because it took more that 16 gigabytes of ram.

So it is impossible to even produce the VHDL-Code for an FFT greater
than 65536 with my computer, because this problem appears then using
toVHDL() or toVerilog(), too.

I think the problem is the great number of Signal()s of intbv()s that
are needed in this design.

Is there another way to describe a synchronous dual port ram that
doesn't need that much memory or can I speed it up another way? Using
another interpreter like pypy or so?

Or is there a way to have a signal-list instead of a list of signals?

Thanks in advance


Regards,

Frederik