Re: [myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

Hi Chris,

it works now. I accidently put a reset_n into my ports which is not
needed at all - this is clear. That was a problem when I tried the
clocked variant. A classical copy paste error.

Thanks for your help.

I found

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Example 11–3 is exactly what I needed to know.

I can conclude that describing a rom needs a clock input to be
synthesizable in quartus.

My code is now:

def twiddlerom(clk, addr, doutr, douti, N, bitwidth):
    '''
        A rom that holds twiddle factors for a FFT
        addr -- address
        doutr, douti -- data out, real and imaginary
        N -- Number of twiddles
    '''

    LMAX = 2**(bitwidth-1)
    MMAX = 2**(2*bitwidth)

    def getTwiddles(N):
        # ...
        return tuple(ret)


    tmpcontent = getTwiddles(N)
    ram = tmpcontent

    tmp = Signal(intbv(0, min=-MMAX, max=MMAX)[2*bitwidth:])

    #@always_comb # doesn't work in quartus
    #def read():
    #    tmp.next = ram[int(addr)]

    @always(clk.posedge)
    def read():
        tmp.next = ram[int(addr)]

    @always_comb
    def devide():
        doutr.next = tmp[2*bitwidth:bitwidth].signed()
        douti.next = tmp[bitwidth:0].signed()

    return read, devide


Kind regards from Germany,

Frederik