Re: [myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

Hello Chris,

I just tried it without success. Without the extra attributes the rom
was made off logic elements. After I added them to the VHDL code
everything was okay.

Do you have another idea?


Regards,

Frederik

Am 27.03.2012 20:32, schrieb Christopher Felton:
> On 3/27/2012 11:18 AM, Frederik T. wrote:
>> This is the template I found in Quartus II to describe a single port rom:
> <snip>
>> begin
>>
>> 	process(clk)
>> 	begin
>> 	if(rising_edge(clk)) then
>> 		q<= rom(addr);
>> 	end if;
>> 	end process;
>>
>> end rtl;
>>
>> It looks different then the case-when statements.
>> Maybe I should generate VHDL code based on this template.
>>
>>
>> Regards,
>>
>> Frederik
>>
> 
> I haven't tested/tried.  You should be able to use the "clocked" 
> generator in your MyHDL code for the read port and get similar generated 
> VHDL that Quartus should recognize as a ROM.  Instead of the always_comb 
> in the read port use a always(clk.posedge).
> 
> Hope that helps,
> Chris
> 
> 
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