Re: [myhdl-list] initial blocks in Verilog

[Christopher F. <chr...@gm...>]

On 3/23/2012 5:21 AM, John Sager wrote:
> I note this as an open task. It bit me trying to co-simulate code in Icarus.
> Essentially the presence of 'undefined' states at the beginning of a simulation
> can give incorrect results. For example an integrator may have its register
> initialised by a reset in the logic, but in simulation, if it receives an
> 'undefined' input, that will propagate into the register and never change
> thereafter! In real logic, depending on circumstance, it may not be necessary to
> reset everything and incur the logic overhead to do that. Undefined (or
> actually, defined by switch-on transients but unknown) states in a pipeline, for
> example, will flush out eventually.
>
> I've added a simple function to _toVerilog.py, modelled on _writeSigDecls, which
> initialises variables in the siglist to the stored value, and initialises RAM in
> memlist to zero with a for loop. Signals of enums are set to zero, as there is
> no obvious initial value for them. Code including initial blocks generated by
> this addition has compiled successfully in Altera's Quartus II web edition.
>
> The open task description talks about dealing with lists of signals and intbvs.
> I'm not sure what else is required to do that though, so this addition may need
> more work.
>

Thanks for the post John,

Not sure if you simply wanted to share some changes that you have made 
or if you want to provide a patch for a future release.  If the later is 
the case you will want to review the following,

http://www.myhdl.org/doku.php/dev:patches

For this task is sounds like you tested the main open item, Quartus 
support of initialized values.  To address close this issue the 
following would need to be completed:

   * VHDL initial value and Verilog.
   * testing other synthesis (others probably can assist).
   * test cases to include in the unit testing.

Regards,
Chris