[myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

Hello all together,

I have a problem with a rom that holds precalculated twiddle factors for
a r2²sdf-pipeline-fft.

I took the rom from the examples directory and changed it and changed it:

def twiddlerom(doutr, douti, addr, N, bitwidth):
    '''
        A rom that holds twiddle factors for a FFT
        doutr, douti-- data out, real and imaginary
        addr -- address
        N    -- Number of twiddles

        Append:
        attribute romstyle : string;
        attribute romstyle of tmp : signal is "M9K";
    '''

    LMAX = 2**(bitwidth-1)
    MMAX = 2**(2*bitwidth)

    def getTwiddles(N):
	ret = [ ... ]
        # ...
	
        return tuple(ret)


    tmpcontent = getTwiddles(N)
    ram = tmpcontent

    tmp = Signal(intbv(0, min=-MMAX, max=MMAX)[2*bitwidth:])

    @always_comb
    def read():
        tmp.next = ram[int(addr)]

    @always_comb
    def devide():
        doutr.next = tmp[2*bitwidth:bitwidth].signed()
        douti.next = tmp[bitwidth:0].signed()

    return read, devide

The rom holds complex twiddles that are devided in the devide generator.
If I just output single values the mentioned problem doesnt' disappear.

Simulation works and Xilinx ISE compiles it into a rom. But Quartus uses
logic blocks until I add the following lines into the generated VHDL code:

attribute romstyle : string;
attribute romstyle of q : signal is "M9K";

My questions are if there is a way to describe a rom that syntesizes in
Xilinx ISE and Altera Quartus without adding anything by hand (or code).

Or is there a way to add some lines into the code but not generate the
whole VHDL or Verilog code, e.g.

__vhdl__.addLine(\
"""attribute romstyle : string;
attribute romstyle of q : signal is "M9K";"""

?

If not this would be a great improment I think.


Kind regards

Frederik