[myhdl-list] Lists of signals don't appear in vcd file

[Frederik T. <sp...@ne...>]

Hello everybody,

I have a question concerning lists of signals. Whenever I use a list of
signals I don't see they don't appear in the vcd file created by
traceSignals(), see gtkwave.png .

An example:

def shiftregister(clk, reset_n, en, din, dout, N, bitwidth):
    '''
        clk     -- clock
        reset_n -- low active reset
        en      -- enable, high active
        din     -- data in
        div     -- data in valid
        dout    -- data out
        dov     -- data out valid
        N       -- number of registers
    '''

    LMAX = 2**(bitwidth-1)

    regs = [Signal(intbv(0, max=LMAX, min=-LMAX)) for ii in range(N)]

    @always(clk.posedge, reset_n.negedge)
    def rtl():
        if reset_n == 0:
            for ii in range(N):
                regs[ii].next = 0
        else:
            if en:
                for ii in range(N-1):
                    regs[ii+1].next = regs[ii]

                regs[0].next = din

    @always_comb
    def comb():
        dout.next = regs[N-1]

    return rtl, comb

>% >% >% >% >% >% >% >%

bitwidth = 16
N = 4

tb = traceSignals(testBenchshiftregister, N, bitwidth)
sim = Simulation(tb)
sim.run()

If I add the signals

reg1, reg2, reg3, reg4 = [Signal(intbv(0, max=LMAX, min=-LMAX)) for ii
in range(N)] # N is 4

the signals appear in the vcd file like in gtkwave2.png .

So what am I doing wrong? Using lists of signals is more generic than
the other way but obiously not debuggable.


Kind regards

Frederik