Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Norbo <Nor...@gm...>]

I Just created a very simple and draft myhdl Version of Migen:
But i think splitting combinatorical and seqential statments up and slice  
them into further smaller statments, doesnt really makes it easy to  
comprehend what is done in the code. But probably with the power of the  
human brain nearly anything is possible.


 from myhdl import *

   comb=[]
   sync=[]
   localSignals=[]
   resetValues=[]

   ######### signal definitioons for startup ############
   localSignals+=["adrs=Signal(intbv(0)[24:])"]
   resetValues+=["adrs.next=0"]


   ##### combinatorial statments #############
   comb+=["if sel==0: out.next=0"]
   comb+=["if sel==1: out.next=1"]
   comb+=["adr.next=adrs"]

   ##### synchronus statments #############
   sync+=["if en: adrs.next=adrs+1"]





   source_text="""def TOP(clk,rst,out,adr,sel,en):
   """+"\n ".join(localSignals)+"""
   @always_comb
   def comb_logic():
     """+"\n   ".join(comb)+"""

   @always(clk.posedge,rst.negedge)
   def seq_logic():
     if rst==0:
       """+"\n     ".join(resetValues)+"""
     else:
       """+"\n     ".join(sync)+"""

   return seq_logic,comb_logic"""

   source_file=open("sourcetext.txt","w")
   source_file.write(source_text)
   source_file.close()
   dd=compile(source_text,"sourcetext.txt","exec")
   exec(dd)

   def test_bench():
       clk=Signal(bool(0))
       rst=Signal(bool(0))
       out=Signal(intbv(0)[4:])
       adr=Signal(intbv(0)[24:])
       sel=Signal(bool(0))
       en=Signal(bool(0))
       instanc_top=TOP(clk,rst,out,adr,sel,en)
       #toVHDL(TOP,clk,out,sel,en)

       @always(delay(10))
       def clkgen():
	  clk.next = not clk


       @instance
       def stimulus():
	rst.next=0
	yield clk
	rst.next=1
	sel.next=0
	yield clk
	yield clk
	print "Value of Output is", out
	sel.next=1
	en.next=1
	yield clk
	yield clk
	print "Value of Output is", out
	for i in range(40):
	  yield clk
	  print "adr Value:", adr
	raise StopSimulation

       return  stimulus,clkgen,instanc_top


   if __name__ == '__main__':
       hello_inst = test_bench()
       sim = Simulation(hello_inst)
       sim.run()