Re: [myhdl-list] Migen logic design toolbox - now with simulator
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From: Jan D. <ja...@ja...> - 2012-03-21 16:54:06
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On 03/21/2012 10:51 AM, Sébastien Bourdeauducq wrote: > On 03/21/2012 10:43 AM, Sébastien Bourdeauducq wrote: >> comb += [If(a[i], pos.eq(i)) for i in downrange(a.bv.width)] > > Of course, it should be "range" here, not "downrange". Apart from my other, more fundamental objections: no, not OK. In a circuit that checks the MSB position I want to check the MSB first, and set the position once by stopping as soon as it is found. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |