Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Jan D. <ja...@ja...>]

On 03/21/2012 10:43 AM, Sébastien Bourdeauducq wrote:
> Hi,
>
> On 03/19/2012 01:30 PM, Jan Decaluwe wrote:
>>> If you are talking about VHDL variables / blocking Verilog assignments
>>> that can be used to synthesize sequential code that "executes" in one
>>> cycle, then they are supported too (with the "variable" property of the
>>> Signal object).
>>
>> That is what I call "horrible". These things are confusing enough,
>> even in VHDL that makes a clear distinction between signals
>> and variables. MyHDL improves further on this by using a
>> dedicated, distinctive attribute assignment for Signal
>> assignment.
>
> Well, it's just a small detail, no need to break such a fuss about it.

Only someone with too much Verilog exposure could say that.

The confusion about this small detail (because of the way Verilog
handles it) is the single most important cause of why HDL-based
design doesn't live up to its potential. As you know, in Verilog,
procedural techniques are virtually banned from clocked processes,
for no good reason except the confusion about this "detail".

> What would you propose then? replace the "variable" property simply with
> the use of a different assignment? or enforce that another assignment
> method is used when the "variable" property is set?

If it's such a small detail, I don't see why you want to
take HDL design lessons from me.

>> def MsbDetector(pos, a):
>>        """Return the bit position of the msb."""
>>
>>        @always_comb
>>        def logic():
>>            pos.next = 0
>>            for i in downrange(len(a)):
>>                if a[i] == 1:
>>                    pos.next = i
>>                    break
>>
>>        return logic
>
> (...)
>
>> How would this look like in Migen?
>
> comb += [If(a[i], pos.eq(i)) for i in downrange(a.bv.width)]

Did you simulate this?

Because I think you missed the break, didn't you? Of course,
I can't tell for sure because who knows how you handle the
statement order in that list.

I will give a free language (*any* language) design tip then:
when the statement order matters, it should visually stand out.
Of course it should.

> Notes:
> 1. the default 0 is implicit (reset value of a combinatorial signal)
> 2. you can build the pos signal with the right size using bits_for:
> pos = Signal(BV(bits_for(a.bv.width-1)))
> 3. we should add len() support for signals, thanks for the reminder :)
> 4. you can either assume the synthesizer will automagically build an
> optimized structure (it doesn't always), or use a bit more control, as in:
> http://www.ohwr.org/projects/tdc-core/repository/revisions/master/entry/core/tdc_lbc.vhd
> It's VHDL, but you could do the same with Migen too.
>
>> So far for elegance
>
> One line :)

Execpt it doesn't work I think.

And since when are one-liners synonymous to elegance? Often
they are the opposite: obfuscation that leads to hard-to-catch
errors, as in this case.

>> and parametrizability.
>
> In this example, it's just as parametrizable as yours. In general, Migen
> is more parametrizable than MyHDL.

That must be true, for those who like to break up their design into
concurrent statements themselves. I prefer to leave that work
to a synthesis tool.

>  Let's have another simple example:
> how would you parametrize the number of wait states (removing them
> entirely when the parameter is 0) at different points of a FSM?

A wait state and a wait state counter with a variable end count.

>> Well, no. Look at the test bench code versus Migen code and
>> note that the modeling paradigm is entirely different.
>> But in practice, today's high-level model that is part
>> of the verification environment becomes tomorrow's
>> synthesizable model and vice versa.
>
> Following the same logic, you could say that all hardware and software
> designs should be written using high level languages such as Python,
> Ruby or Lisp normally, and hope that one day some magical synthesizer
> will make them fast and optimized on FPGA, ASIC and CPU. Given that Lisp
> is still slow more than 50 years after its invention, let me have doubts
> about this position.

I am not talking about the uncertain future either. I am talking
about models that are not initially intended for synthesis, and evolve
to that requirement later.

> Or you can be pragmatic and do things like Migen.
>
>> Very often, this even happens within the same project.
>
> Can you give some examples?

Virtually any telecom chip where the TX side is verified by
looping back the RX side and vice versa.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com