Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Sébastien B. <seb...@mi...>]

Hi,

On 03/19/2012 01:30 PM, Jan Decaluwe wrote:
>> If you are talking about VHDL variables / blocking Verilog assignments
>> that can be used to synthesize sequential code that "executes" in one
>> cycle, then they are supported too (with the "variable" property of the
>> Signal object).
>
> That is what I call "horrible". These things are confusing enough,
> even in VHDL that makes a clear distinction between signals
> and variables. MyHDL improves further on this by using a
> dedicated, distinctive attribute assignment for Signal
> assignment.

Well, it's just a small detail, no need to break such a fuss about it. 
What would you propose then? replace the "variable" property simply with 
the use of a different assignment? or enforce that another assignment 
method is used when the "variable" property is set?

> def MsbDetector(pos, a):
>       """Return the bit position of the msb."""
>
>       @always_comb
>       def logic():
>           pos.next = 0
>           for i in downrange(len(a)):
>               if a[i] == 1:
>                   pos.next = i
>                   break
>
>       return logic

(...)

> How would this look like in Migen?

comb += [If(a[i], pos.eq(i)) for i in downrange(a.bv.width)]

Notes:
1. the default 0 is implicit (reset value of a combinatorial signal)
2. you can build the pos signal with the right size using bits_for:
pos = Signal(BV(bits_for(a.bv.width-1)))
3. we should add len() support for signals, thanks for the reminder :)
4. you can either assume the synthesizer will automagically build an 
optimized structure (it doesn't always), or use a bit more control, as in:
http://www.ohwr.org/projects/tdc-core/repository/revisions/master/entry/core/tdc_lbc.vhd
It's VHDL, but you could do the same with Migen too.

> So far for elegance

One line :)

> and parametrizability.

In this example, it's just as parametrizable as yours. In general, Migen 
is more parametrizable than MyHDL. Let's have another simple example: 
how would you parametrize the number of wait states (removing them 
entirely when the parameter is 0) at different points of a FSM?

> Well, no. Look at the test bench code versus Migen code and
> note that the modeling paradigm is entirely different.
> But in practice, today's high-level model that is part
> of the verification environment becomes tomorrow's
> synthesizable model and vice versa.

Following the same logic, you could say that all hardware and software 
designs should be written using high level languages such as Python, 
Ruby or Lisp normally, and hope that one day some magical synthesizer 
will make them fast and optimized on FPGA, ASIC and CPU. Given that Lisp 
is still slow more than 50 years after its invention, let me have doubts 
about this position.

Or you can be pragmatic and do things like Migen.

> Very often, this even happens within the same project.

Can you give some examples?

Sébastien