[myhdl-list] Convertion to Verilog inout port

[Wesley N. <we...@sk...>]

Hi All,

I need myhdl to generate an inout port for my toplevel verilog as we have a
bus with bidirectional data lines between our FPGA and CPU.

I am using user_defined code so there is no way that MyHDL can infer that
the port must be inout.

How would I go about doing this?

Thanks

Wesley