Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Jan D. <ja...@ja...>]

On 03/19/2012 10:06 AM, Sébastien Bourdeauducq wrote:

> If you are talking about VHDL variables / blocking Verilog assignments
> that can be used to synthesize sequential code that "executes" in one
> cycle, then they are supported too (with the "variable" property of the
> Signal object).

That is what I call "horrible". These things are confusing enough,
even in VHDL that makes a clear distinction between signals
and variables. MyHDL improves further on this by using a
dedicated, distinctive attribute assignment for Signal
assignment.

Verilog is much worse, because it doesn't make the distinction
between signals and variables. But at least it uses
two different types of assignment. Unfortunately, this is
not enough for most Verilog designers to get the
difference.

But Migen uses the same type of assignment for 2 things
which semantically could not be more different, and
hides that difference in an object constructor. No
excuses here. This is horrible!

Apart from all this, and even more importantly, what
is missing is support for typical procedural modeling.
Consider the following combinatorial circuit in MyHDL:

def MsbDetector(pos, a):
     """Return the bit position of the msb."""

     @always_comb
     def logic():
         pos.next = 0
         for i in downrange(len(a)):
             if a[i] == 1:
                 pos.next = i
                 break

     return logic

I think it is hard to argue about the elegance and
clarity of the description. Moreover, it is
parametrizable for any bit width by default.

How would this look like in Migen? Some elaborate
if-then-else structure that explicitly lists all
the cases. Moreover, the structure size would depend
on the actual bit width. So far for elegance and
parametrizability.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com