Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Sébastien B. <seb...@mi...>]

On 03/18/2012 11:10 PM, Jan Decaluwe wrote:
> With "procedural support" I am not referring to procedures.
> Rather, I am using the word "procedural" to refer to statements whose
> order matters, as opposed to "concurrent" statements. The VHDL
> terminology is "sequential" but this word can be confusing also
> (as it also used to refer to clocked behavior.)

If you are talking about VHDL variables / blocking Verilog assignments 
that can be used to synthesize sequential code that "executes" in one 
cycle, then they are supported too (with the "variable" property of the 
Signal object).

For sequential test bench code, you can use e.g. Python generators as in 
the Wishbone example from the doc.

Anything else that I missed?

Sébastien