Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Jan D. <ja...@ja...>]

On 03/17/2012 02:15 AM, Sébastien Bourdeauducq wrote:
> On 03/16/2012 10:03 PM, Jan Decaluwe wrote:
>> When Migen claims that the "event-driven" paradigm is
>> too general, what it really dumps is procedural support
>> in your HDL descriptions - the interesting stuff.
>
> This isn't entirely fair (I will not even mention the impolite bits
> above). First, procedures in V*HDL can often be easily converted to bits
> of Python code that manipulate the lower layer bits - admittedly in a
> less elegant way (though perhaps easier to understand), but it can be
> done. Second, for synthesis those procedures always need to "execute" in
> one clock cycle, which seriously limits their real usefulness.

With "procedural support" I am not referring to procedures.
Rather, I am using the word "procedural" to refer to statements whose
order matters, as opposed to "concurrent" statements. The VHDL
terminology is "sequential" but this word can be confusing also
(as it also used to refer to clocked behavior.)

>  Also,
> this while thing has little to do with event-driven vs. cycle-based.

The relevant feature is whether events are explicit (VHDL, Verilog, MyHDL)
or implicit (Migen et al). In practice, all HDLs with explicit events
that I know of support procedural semantics, and none of the HDLs
with implicit events that I know of do so.

In particular, Migen has concurrent semantics only. The lack of
procedural semantics is a showstopper.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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