Re: [myhdl-list] CASPER/UC Berkley is considering MyHDL

[Wesley N. <we...@sk...>]

Hi Guys,

This is a project that I am trying to get going, the most active fork is
the one Chris linked: https://github.com/wnew/hdl_devel But Ill hope to
push it to the master at https://github.com/casper-astro/hdl_devel soon.

Here is a brief overview for anyone who is interested:

We are using simulation and verification functionality that MyHDL provides
thought Python, to model hardware designs. We are creating highly
parameterised verilog cores and wrapping them with a layer of Python. These
serve as the building blocks for designs, each block providing a simulation
model and glue logic in Python. This is all brought together by the
framework which will implement functionality such as automatic bus
management and also manage clock domains. Ultimately a block diagram based
GUI will be used to create designs. The aim is to be able to support any
vendor and provide the designer with a "one-click" compile solution.

Regards

Wes

On Tue, Mar 13, 2012 at 6:21 AM, Christopher Felton
<chr...@gm...>wrote:

> On 3/12/12 10:16 PM, Karl Kaiser wrote:
> > Dear all,
> >
> > I thought this may be interesting for this list:
> >
> > https://casper.berkeley.edu/wiki/MyHDL_toolflow
> >
> > Enjoy,
> > Karl
> >
> >
> Thanks for the post Karl.  There has been some development efforts by
> different Casper contributors started,
>
>   https://github.com/wnew/hdl_devel
>
> There are a couple active development branches I lost track which one is
> the most active (github fork view will some info).
>
> Regards,
> Chris
>
>
>
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