Re: [myhdl-list] Adder/Subtractor design

[John S. <jo...@sa...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

...
> 
> Couple things, If you want a single module that is an adder/subtractor 
> you can directory add or subtract.
> 
> def AdderSubtractor(clk, a,b,c, Subtract=False):
>      assert len(a) >= max(len(b),len(c))+1
>      @always(clk.posedge)
>      def hdl_add_sub():
>          if Subtract:	
> 	    c.next = a - b
>          else:
>              c.next = a + b
> 
>      return hdl_ad_sub
> 
> The above is completely scalable for the different bit widths.  You 
> might not need to define a AdderSubtractor module just use '+' and '-' 
> unless you are multiplexing the adder/subtractor in the datapath.
>
...
> 
> Regards,
> Chris

In fact I started off with the if-then-else construct on the Subtract flag but I
thought that the xor/plus logic would be more efficient. I ran them both through
the Quartus II compiler (Cyclone III target) yesterday and I found that the
circuit design using if-then-else uses considerably less logic for the same
functionality (on the complete circuit which instantiates many add/subtract
functions). That was completely against my expectation, but then I'm a long-time
software guy just starting out with hardware design.

To that end I'm finding Myhdl to be an excellent tool to help me get to grips
with it all.

J