Re: [myhdl-list] Adder/Subtractor design

[Christopher F. <chr...@gm...>]

On 3/4/12 11:37 AM, John Sager wrote:
> Christopher Felton<chris.felton<at>  gmail.com>  writes:
>
>>>
>>> Jan,
>>>
>>> Thanks for that. However it's a bit low level, really, having to
>>> synthesise an adder from basic logic rather than using Verilog's
>>> higher level operators. The useful thing in that was the
>>> ConcatSignal(*x) Python parameter passing idiom, of which I wasn't
>>> aware, which would have saved me the hack on _ShadowSignal.py
>>>
>>> John
>>>
>>>
>>
>> Wait, that's contradictory to this thread.  If you don't want to
>> represent low-level description (which is good) simply use "c = a+b" you
>> don't need to worry about anything else.  The synthesis tools will
>> gladly create correct/valid adders.
>>
>> Regards,
>> Chris
>>
>
> The real question I asked was whether myhdl would support generating the
> {n{flag}} construct to produce 'cleaner' Verilog.
>
> what I get out is something like
>
> wire [15:0] x;
>
> assign x[15] = flag;
> assign x[14] = flag;
> ...
> assign x[1] = flag;
> assign x[0] = flag;
>
> and then used in
>
> a<= b + c^x + flag
>
> I suppose I shouldn't really worry about what the Verilog looks like. My code
> simulates correctly in both myhdl and co-simulated with Icarus now anyway.
>
> J

The goal of MyHDL is not make "clean" looking Verilog/VHDL (as in clean 
to the human reader) but Verilog and VHDL are the intermediate formats 
that the syntehsizers understand (optimized for syntheized results).  In 
an ideal flow the MyHDL created Verilog/VHDL would not need to be looked 
at (by a human).  With that said the Verilog/VHDL is not obfuscated if 
it doesn't need to be.

Couple things, If you want a single module that is an adder/subtractor 
you can directory add or subtract.

def AdderSubtractor(clk, a,b,c, Subtract=False):
     assert len(a) >= max(len(b),len(c))+1
     @always(clk.posedge)
     def hdl_add_sub():
         if Subtract:	
	    c.next = a - b
         else:
             c.next = a + b

     return hdl_ad_sub

The above is completely scalable for the different bit widths.  You 
might not need to define a AdderSubtractor module just use '+' and '-' 
unless you are multiplexing the adder/subtractor in the datapath.

Second, I think the problem here is trying to write the MyHDL in a 
Verilog form.  Best I can tell from the question you want to find away 
to initialize a bit-vector, that is variable size, either set it to all 
0s or all 1s.

all 0s: vec = Signal(intbv(0)[N:])
all 1s: vec = Signal(intbv(2**N-1)[N:])

Or you could use the ConcatSignal or concat

   x = concat(*[intbv(1)[1:] for ii in range(N)])
or
   x = ConcatSignal(*[Signal(True) for ii in range(N)])

No hacking required :)

Regards,
Chris