Re: [myhdl-list] Adder/Subtractor design
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From: John S. <jo...@sa...> - 2012-03-04 17:37:40
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Christopher Felton <chris.felton <at> gmail.com> writes: > > > > Jan, > > > > Thanks for that. However it's a bit low level, really, having to > > synthesise an adder from basic logic rather than using Verilog's > > higher level operators. The useful thing in that was the > > ConcatSignal(*x) Python parameter passing idiom, of which I wasn't > > aware, which would have saved me the hack on _ShadowSignal.py > > > > John > > > > > > Wait, that's contradictory to this thread. If you don't want to > represent low-level description (which is good) simply use "c = a+b" you > don't need to worry about anything else. The synthesis tools will > gladly create correct/valid adders. > > Regards, > Chris > The real question I asked was whether myhdl would support generating the {n{flag}} construct to produce 'cleaner' Verilog. what I get out is something like wire [15:0] x; assign x[15] = flag; assign x[14] = flag; ... assign x[1] = flag; assign x[0] = flag; and then used in a <= b + c^x + flag I suppose I shouldn't really worry about what the Verilog looks like. My code simulates correctly in both myhdl and co-simulated with Icarus now anyway. J > ------------------------------------------------------------------------------ > Virtualization & Cloud Management Using Capacity Planning > Cloud computing makes use of virtualization - but cloud computing > also focuses on allowing computing to be delivered as a service. > http://www.accelacomm.com/jaw/sfnl/114/51521223/ > |