Re: [myhdl-list] Adder/Subtractor design
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From: Jan C. <jan...@mu...> - 2012-03-04 13:12:14
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On 04/03/12 07:27, John Sager wrote: > Jan Coombs<jan.coombs_2009<at> murray-microft.co.uk> writes: > >> >> On 03/03/12 16:40, John Sager wrote: >> . . . >> > >> > Now the question: Is there any facility in Myhdl to generate the >> {n{Sub}} >> > construct, and with a correct simulation? >> >> http://rosettacode.org/wiki/Four_bit_adder#MyHDL >> >> The second code sample here is Jan D's, and looks good to me. >> >> Jan Coombs. >> > > Jan, > > Thanks for that. However it's a bit low level, really, having to > synthesise an adder from basic logic rather than using Verilog's > higher level operators. The useful thing in that was the > ConcatSignal(*x) Python parameter passing idiom, of which I wasn't > aware, which would have saved me the hack on _ShadowSignal.py Sorry, replace the three defs in with: def Multibit_Adder(a, b, s): @always_comb def add(): s.next = a + b return add This seems to sim & convert ok. It was late and I assumed that breaking the signals into individual bits would be necessary, but it is not. Jan Coombs. |