Re: [myhdl-list] Adder/Subtractor design

[John S. <jo...@sa...>]

Jan Coombs <jan.coombs_2009 <at> murray-microft.co.uk> writes:

> 
> On 03/03/12 16:40, John Sager wrote:
>     . . .
>  >
>  > Now the question: Is there any facility in Myhdl to generate the 
> {n{Sub}}
>  > construct, and with a correct simulation?
> 
> http://rosettacode.org/wiki/Four_bit_adder#MyHDL
> 
> The second code sample here is Jan D's, and looks good to me.
> 
> Jan Coombs.
> 

Jan,

Thanks for that. However it's a bit low level, really, having to
synthesise an adder from basic logic rather than using Verilog's
higher level operators. The useful thing in that was the
ConcatSignal(*x) Python parameter passing idiom, of which I wasn't
aware, which would have saved me the hack on _ShadowSignal.py

John