[myhdl-list] Adder/Subtractor design

[John S. <jo...@sa...>]

The standard logic expression for an adder/subtractor is

a = b + c^d + Sub

where d is a vector of length len(c) and where each bit takes the value of the
Sub signal. In Verilog this would be

a <= b + c ^ {n{Sub}} + Sub where n is len(c) and a, b & c are signed quantities.

I've managed to do something similar in Myhdl (v0.7) as follows

def foo(clk, a, b, c, Sub):

  x=[]
  for i in range(len(c)):
    x.append(Sub)  # Sub is a Signal
  vec = ConcatSignal(x)

  @always(clk.posedge)
  def bar():
    a.next = b + (c.signed()^vec.signed()) + Sub
  return bar

Note that I had to hack on _ShadowSignal.py to enable ConcatSignal to take a
list of signals as the sole parameter as well as the normal way - I need to be
able to change the vector length for different instantiations of the
adder/subtractor.

This will simulate correctly, but the Verilog produced is a bit baroque, and I
haven't yet simulated it, though it looks OK. Essentially 'vec' is a wire of
width len(c) and there are then len(c) assignment statements to assign Sub to
each bit.

Now the question: Is there any facility in Myhdl to generate the {n{Sub}}
construct, and with a correct simulation?

John Sager
john <at> sager <dot> me <dot> uk