Re: [myhdl-list] Restrictions for conversion

[Norbo <Nor...@gm...>]

About: (More general support of indexed constants)  
http://www.myhdl.org/doku.php/dev:tasks
ok this post maybe gets a bit long, but it may be helpful to further  
eliminate this conversion limitation:

i first present a simple myhdl example which is victim to such an  
conversion limitation.
then i show three slightly different ways how it can be implemented in  
vhdl (i dont no verilog).

the myhdl example:

##########################################################################
 from myhdl import *

def somedut(inData,out_data,data_index,LENGTH):
     TWIDDEL_WIDTH=10
     real_Vals=[Signal(intbv(0,min=-2000,max=2000)) for i in range(LENGTH)]
     Table=tuple([i for i in range(LENGTH)])

     @always_comb
     def comb_logic():
       for i in range(LENGTH):
         real_Vals[i].next=inData*Table[i]   ###this line cannot be  
converted to vhdl
     @always_comb
     def output_logic():
         out_data.next=real_Vals[data_index]

     return comb_logic,output_logic #real_alu_insts,imag_alu_insts,  
comb_logic,seq_logic

def TESTBENCH_XX():
     LENGTH=100
     clk=Signal(bool(0))
     inData=Signal(intbv(0,min=-10,max=10))
     out0=Signal(intbv(0,min=-2000,max=2000))
     index=Signal(intbv(0,min=0,max=100))

     toVHDL(somedut,inData,out0,index,LENGTH)
     dut_inst=somedut(inData,out0,index,LENGTH)

     @always(delay(10))
     def clkgen():
         clk.next = not clk

     @instance
     def stimulus():
         index.next=0
         inData.next=0
         inData.next=1
	for i in range(LENGTH):
	  yield clk
	  index.next=i
	
	inData.next=2
	for i in range(LENGTH):
	  yield clk
	  index.next=i	

         raise StopSimulation

     @instance
     def Monitor():
         #print "\t\tPortC:",PORTC_OUT,"Binary:" ,bin(PORTC_OUT,WORD_SZ)
         while 1:
             yield out0
             print "out0=",out0



     return dut_inst,Monitor,stimulus,clkgen

sim = Simulation(TESTBENCH_XX())
sim.run()

##########################################################################
The Error is:
myhdl.ConversionError: in file general_rom.py, line 13:
     Object type is not supported in this context: Table, <type 'tuple'>
##########################################################################



Possible (by altera quartus synthesis able) ways it could be implemented  
in vhdl:
The one with the function is proposed on  
http://www.myhdl.org/doku.php/dev:tasks (More general support of indexed  
constants)
##############################################################################
-- File: TESTBENCH.vhd
-- Generated by MyHDL 0.7
-- Date: Sat Feb 18 19:09:25 2012


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_07.all;

entity TESTBENCH is
       port (
		  clk : in std_logic;
         inData: in signed (4 downto 0);
         out_data: out signed (7 downto 0);
         data_index: in signed (7 downto 0)
		
     );
end entity TESTBENCH;


architecture MyHDL of TESTBENCH is


type t_array_dut_inst_real_Vals is array(0 to 16) of signed (15 downto 0);
signal dut_inst_real_Vals: t_array_dut_inst_real_Vals;




type t_array_dut_test is array(0 to 16) of signed (4 downto 0);
---- 1. solution (solution 1 and 2 is basically the same but in sulotion 1  
the content of the array is built
---- programtically)
function init_mem return t_array_dut_test is
     variable temp_mem : t_array_dut_test;
begin
     for i in t_array_dut_test'range loop
         temp_mem(i) := to_signed(i, 5);
     end loop;
     return temp_mem;
end;

signal dut_inst_test: t_array_dut_test:=init_mem;
--or signal dut_inst_test: t_array_dut_test:=init_mem;

---- 2. solution, directly initialize the array
signal dut_inst_test2: t_array_dut_test:=(0=> "00000",
                                             1=> "00001",
                                             2=> "00010",
                                             3=> "00011",
                                             4=> "00100",
					5=> "00101",
					6=> "00110",
					7=> "00111",
					8=> "01000",
					9=> "01001",
					10=> "01010",
					11=> "01011",
					12=> "01100",
					13=> "01101",
					14=> "01110",
					15=> "01111",
					others => "10000");


---- 3. solution same as Rom in myhdl, but from a function
function ValueSelect(dut_inst_RomAddr: in integer) return signed is
     variable dut_inst_RomData : signed (4 downto 0);
begin
     case dut_inst_RomAddr is
         when 0 => dut_inst_RomData := "00000";  --attention : instead of <=
         when 1 => dut_inst_RomData := "00001";
		  when 2 => dut_inst_RomData := "00010";
		  when 3 => dut_inst_RomData := "00011";
		  when 4 => dut_inst_RomData := "00100";
		  when 5 => dut_inst_RomData := "00101";
		  when 6 => dut_inst_RomData := "00110";
		  when 7 => dut_inst_RomData := "00111";
		  when 8 => dut_inst_RomData := "01000";
		  when 9 => dut_inst_RomData := "01001";
		  when 10 => dut_inst_RomData :=  "01010";
		  when 11 => dut_inst_RomData :=  "01011";
		  when 12 => dut_inst_RomData :=  "01100";
		  when 13 => dut_inst_RomData :=  "01101";
		  when 14 => dut_inst_RomData :=  "01110";
		  when 15 => dut_inst_RomData :=  "01111";
		  when others => dut_inst_RomData := "10000";
     end case;
   return dut_inst_RomData;
end;





begin

-- combinatorial
TESTBENCH_DUT_INST_COMB_LOGIC: process ( inData,dut_inst_test) is
begin
	
     for i in 0 to 16 loop
         dut_inst_real_Vals(i) <= (resize(inData, 11) * dut_inst_test(i));  
--dut_inst_test2(i)); or ValueSelect(i));
     end loop;
	
end process TESTBENCH_DUT_INST_COMB_LOGIC;



-- clocked
--TESTBENCH_DUT_INST_COMB_LOGIC: process ( clk) is
--begin
--if rising_edge(clk) then
--    for i in 0 to 16 loop
--        dut_inst_real_Vals(i) <= (resize(inData, 11) * ValueSelect(i));  
--dut_inst_test2(i)); or ValueSelect(i));
--    end loop;
--	 end if;
--end process TESTBENCH_DUT_INST_COMB_LOGIC;



out_data <= resize(dut_inst_real_Vals(to_integer(data_index)), 8);



end architecture MyHDL;

##############################################################################

greetings Norbo