[myhdl-list] can MyHDL help?

[Tim B. <tim...@so...>]

Hi,

I've been writing VHDL for Xilinx FPGAs for a few year now. I use the 
standard Xilinx tool including ISIM for simulation.
I've also picked up a bit of python along the way.
Then I found MyHDL. I really like the idea and have installed it and 
gone through some of the examples.

The project I'm currently working is basically a Gigabit Ethernet TCP 
socket to connect to a High speed serial IO. Any data that comes across 
the TCP/IP socket gets sent to the serial IO and vice versa.

Python has dpkt, so I can craft Ethernet, ip, arp, tcp... packets very 
easily. However, it would still involve a little work to craft frames 
dynamically. Much easier than the alternative of doing it in VHDL!
For now I'm making frames with dpkt and saving them to a file and 
reading the file into a VHDL testbench.

Python also has sockets but I can't imaging it would be easy to tell it 
to send and receive packet to the myhdl test bench would it?...

Now I have read that there is not much support for vhdl co simulation, 
and in fact, none for ISIM: it doesn;t have a VHPI interface. However, I 
would be willing to try GHDL if the community thinks it is mature enough 
to have a go with for this application.

What do you think?

Tim
-- 

Senior Design Engineer
Somerdata Ltd
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E-mail: tim...@so...
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