Re: [myhdl-list] List of signals unsupported in top-level

[Wesley N. <we...@sk...>]

Wonderful,

Thanks for the help Chris.


On Thu, Jan 12, 2012 at 3:51 PM, Christopher Felton
<chr...@gm...>wrote:

> On 1/12/2012 6:06 AM, Wesley New wrote:
> > I have been creating the toplevel of my design and while converting to
> > verilog and have come across a problem similar to the one discussed here:
> >
> > http://comments.gmane.org/gmane.comp.python.myhdl/1568
> >
> > to quote Jan:
> >
> > "The problem is that Verilog doesn't permit memories as ports.
> > As my goal is to support both Verilog and VHDL equally, I have
> > to use the lowest common demoninator. Therefore, list of signals
> > as ports are not supported."
> >
> > I have been able to create and synthesize lists of ports in verilog at
> the
> > toplevel without problems, but MyHDL doesnt support this. Is this to do
> > with the version of verilog or am I missing something?
> >
> > So for instance:
> >
> > module toplevel (
> >
> >   ..
> > * output* [ 7:0] gpio
> > ...
> > );
> >
> > This is used along with a UCT file with the following lines:
> >
> > NET "gpio<0>" LOC = G31 | IOSTANDARD = "LVCMOS15"; NET "gpio<1>" LOC =
> H31
> > | IOSTANDARD = "LVCMOS15"; NET "gpio<2>" LOC = AF32 | IOSTANDARD =
> > "LVCMOS15"; NET "gpio<3>" LOC = AG33 | IOSTANDARD = "LVCMOS15"; NET
> > "gpio<4>" LOC = L30 | IOSTANDARD = "LVCMOS15"; NET "gpio<5>" LOC = H30 |
> > IOSTANDARD = "LVCMOS15"; NET "gpio<6>" LOC = M29 | IOSTANDARD =
> "LVCMOS15";
> > NET "gpio<7>" LOC = J30 | IOSTANDARD = "LVCMOS15";
> >
> > And this works with out hassles. But when I use MyHDL...
> >
> > My MyHDL toplevel looks like this:
> >
> > from myhdl import *
> >
> > def toplevel(
> >        sys_clk_n,
> >        sys_clk_p,
> >        gpio,
> >     ):
> >
> >
> > def convert():
> >     sys_clk_n, sys_clk_p = [Signal(bool(0)) for i in range(2)]
> >     # MyHDL doesnt support passing a list of ports
> >     # this is just silently dropped!
> >     gpio = [Signal(intbv(0)[15:]]
>
> You don't need to do this, have gpio be a list, just simply use
>
>    gpio = Signal(intbv(0)[15:])
>
> That should fix the issue.  Note: a list of signals is not support as
> ports.
>
> Hope that helps,
> Chris
>
> >
> >     toVerilog(roach2_base, sys_clk_n, sys_clk_p, gpio)
> >
> > I get and ERROR:  List of signals as a port is not supported: gpio
> >
> > I know verilog doesnt support passing of 2D arrays as ports, but I have
> > definitely used a list of ports (Single dimension array) at the toplevel.
> >
> > Can some help me shed some light on this issue? Am I doing something
> wrong?
> >
> >
> > Regards
> >
> > Wes
> >
> >
> >
> >
> >
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