Re: [myhdl-list] strange behavior on some sample code

[Norbo <Nor...@gm...>]

Am 13.12.2011, 14:25 Uhr, schrieb Christopher Felton  
<chr...@gm...>:

> On 12/12/11 1:40 PM, Norbo wrote:
>> hello
>>
>  > <snip>
>
> If you change the code, slightly it will convert without error.  I did
> not look at the generated VHDL (don't have a VHDL sim/syn on this
> computer).  The example you submitted, doesn't make too much sense
> because the "select" signal is internal to you TOP module.  Essentially
> the circuit being described would have no inputs, hence the
> "_error.EmptySensitivityList" error.
>
> Hope this helps,
> Chris
>
> ~~~~~[ Modified code ]~~~~
> from myhdl import *
> from random import randrange
>
> ENUM_TYPE = enum('GIVE_ONE', 'GIVE_TWO')
>
> def TOP(outvalue, sel_value):
>
>      @always_comb
>      def combi_sel():
>          if sel_value == ENUM_TYPE.GIVE_ONE :
>              outvalue.next=1
>          elif sel_value == ENUM_TYPE.GIVE_TWO :
>              outvalue.next=2
>
>      return instances()
>
>
> def test_bench():
>      outsignal=Signal(intbv(0)[4:])
>      sel_value=Signal(ENUM_TYPE.GIVE_TWO)
>      instanc_top=TOP(outsignal, sel_value)
>
>      interval = delay(10)
>      @instance
>      def stimulus():
>          sel_value.next = ENUM_TYPE.GIVE_TWO
>          yield delay(1)
>          print "Value of Output is", outsignal
>          sel_value.next = ENUM_TYPE.GIVE_ONE
>          yield delay(1)
>          print "Value of Output is", outsignal
>
>          raise StopSimulation
>
>      return stimulus,instanc_top
>
>
> if __name__ == '__main__':
>      hello_inst = test_bench()
>
>      sim = Simulation(hello_inst)
>      print "-"*30 + "Simulation Started" + "-"*30
>      sim.run(10)
>      print "-"*30 + "Simulation Finished" + "-"*30
>
>
>      outsignal=Signal(intbv(0)[4:])
>      sel_value=Signal(ENUM_TYPE.GIVE_TWO)
>
>      print "-"*30 + "Conversion To VHDL Started" + "-"*30
>      toVHDL(TOP,outsignal, sel_value)

the Thing is that if a bool or a intbv is used the code in exactly the  
same manner, it works.
For me the ability to put a konstant signal inside the module seems to be  
quite usefull in some cases.

In the following there are some cases which might show some  
inconsistencies.
The case that the bool is comparable with a intbv of 1 bit length would  
may just be a nice to have. ;)

------------------------------------
def TOP(outvalue):
     sel_value=Signal(bool(0))

     @always_comb
     def combi_sel():
       if sel_value == bool(0) :
	outvalue.next=1
       elif sel_value == bool(1) :
	outvalue.next=2

     return instances()

Simulation Works, Conversion to VHDL Works, and Synthesis of VHDL Works
------------------------------------


------------------------------------
def TOP(outvalue):
     sel_value=Signal(bool(0))

     @always_comb
     def combi_sel():
       if sel_value == 0 :
	outvalue.next=1
       elif sel_value == 1 :
	outvalue.next=2

     return instances()

Simulation Works, Conversion to VHDL Fails!! (TypeError: Unexpected type)  
Conversion to Verilog same Error
------------------------------------


------------------------------------
def TOP(outvalue):
     sel_value=Signal(bool(0))

     @always_comb
     def combi_sel():
       if sel_value == 0 :
	outvalue.next=1
       elif sel_value == bool(1) :
	outvalue.next=2

     return instances()

Simulation Works, Conversion to VHDL Works, and Synthesis of VHDL Works!!
------------------------------------


------------------------------------
def TOP(outvalue):
     sel_value=Signal(intbv(0)[1:])

     @always_comb
     def combi_sel():
       if sel_value == 0 :
	outvalue.next=1
       elif sel_value == 1 :
	outvalue.next=2

     return instances()

Simulation Works, Conversion to VHDL Works, Synthesis VHDL Works!!
------------------------------------



------------------------------------
def TOP(outvalue):
     sel_value=Signal(intbv(0)[1:])

     @always_comb
     def combi_sel():
       if sel_value == bool(0) :
	outvalue.next=1
       elif sel_value == bool(1) :
	outvalue.next=2

     return instances()

Simulation Works, Conversion to VHDL Works, Synthesis of VHDL Fails (No  
matching overload for "=") !!
Synthesis of Veriolog Works !!
------------------------------------


------------------------------------
def TOP(outvalue):
     sel_value=Signal(intbv(0)[1:])

     @always_comb
     def combi_sel():
       if sel_value == 0 :
	outvalue.next=1
       elif sel_value == bool(1) :
	outvalue.next=2

     return instances()

Simulation Works, Conversion to VHDL Works, Synthesis of VHDL Fails (No  
matching overload for "=") !!
------------------------------------

------------------------------------
ENUM_TYPE = enum('GIVE_ONE', 'GIVE_TWO')

def TOP(outvalue):
     sel_value=Signal(ENUM_TYPE.GIVE_ONE)

     @always_comb
     def combi_sel():
       if sel_value == ENUM_TYPE.GIVE_ONE:
	outvalue.next=1
       elif sel_value == ENUM_TYPE.GIVE_TWO :
	outvalue.next=2

     return instances()

Simulation Works, Conversion to VHDL Fails with error:

Traceback (most recent call last):
   File "Case2.py", line 45, in <module>
     toVHDL(TOP,outsignal)
   File  
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py", line  
165, in __call__
     _convertGens(genlist, siglist, vfile)
   File  
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py", line  
392, in _convertGens
     assert 0
AssertionError


Conversion to Veriolog Fails with:

Traceback (most recent call last):
   File "Case2.py", line 45, in <module>
     toVerilog(TOP,outsignal)
   File  
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVerilog.py",  
line 149, in __call__
     _writeSigDecls(vfile, intf, siglist, memlist)
   File  
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVerilog.py",  
line 291, in _writeSigDecls
     print >> f, "assign %s = %s;" % (s._name, int(s._val))
TypeError: int() argument must be a string or a number, not 'EnumItem'
------------------------------------