Re: [myhdl-list] strange behavior on some sample code

[Christopher F. <chr...@gm...>]

On 12/12/11 1:40 PM, Norbo wrote:
> hello
>
 > <snip>

If you change the code, slightly it will convert without error.  I did 
not look at the generated VHDL (don't have a VHDL sim/syn on this 
computer).  The example you submitted, doesn't make too much sense 
because the "select" signal is internal to you TOP module.  Essentially 
the circuit being described would have no inputs, hence the 
"_error.EmptySensitivityList" error.

Hope this helps,
Chris

~~~~~[ Modified code ]~~~~
from myhdl import *
from random import randrange

ENUM_TYPE = enum('GIVE_ONE', 'GIVE_TWO')

def TOP(outvalue, sel_value):

     @always_comb
     def combi_sel():
         if sel_value == ENUM_TYPE.GIVE_ONE :
             outvalue.next=1
         elif sel_value == ENUM_TYPE.GIVE_TWO :
             outvalue.next=2

     return instances()


def test_bench():
     outsignal=Signal(intbv(0)[4:])
     sel_value=Signal(ENUM_TYPE.GIVE_TWO)
     instanc_top=TOP(outsignal, sel_value)

     interval = delay(10)
     @instance
     def stimulus():
         sel_value.next = ENUM_TYPE.GIVE_TWO
         yield delay(1)
         print "Value of Output is", outsignal
         sel_value.next = ENUM_TYPE.GIVE_ONE
         yield delay(1)
         print "Value of Output is", outsignal

         raise StopSimulation

     return stimulus,instanc_top


if __name__ == '__main__':
     hello_inst = test_bench()

     sim = Simulation(hello_inst)
     print "-"*30 + "Simulation Started" + "-"*30
     sim.run(10)
     print "-"*30 + "Simulation Finished" + "-"*30


     outsignal=Signal(intbv(0)[4:])
     sel_value=Signal(ENUM_TYPE.GIVE_TWO)

     print "-"*30 + "Conversion To VHDL Started" + "-"*30
     toVHDL(TOP,outsignal, sel_value)