Re: [myhdl-list] strange behavior on some sample code

[Norbo <Nor...@gm...>]

hello

lets say e.g i have written code like:


########################Case 1: (code)#####################
 from myhdl import *
 from random import randrange


def TOP(outvalue):

     sigTest=Signal(intbv(0)[4:])
     @always_comb
     def comb_setConst():
       sigTest.next=4

     @always_comb
     def combi_sel():
       if sigTest == 1:
	outvalue.next=1
       elif sigTest == 4:
	outvalue.next=2

     return instances()


def test_bench():
     outsignal=Signal(intbv(0)[4:])
     instanc_top=TOP(outsignal)

     interval = delay(10)
     @always(interval)
     def stimulus():
         print "Value of Output is", outsignal

     return  stimulus,instanc_top


if __name__ == '__main__':
     hello_inst = test_bench()
     sim = Simulation(hello_inst)
     sim.run(10)

     outsignal=Signal(intbv(0)[4:])
     toVHDL(TOP,outsignal)
#############################################################



####################Console Output:#################################
Traceback (most recent call last):
   File "notDriven.py", line 39, in <module>
     hello_inst = test_bench()
   File "notDriven.py", line 28, in test_bench
     instanc_top=TOP(outsignal)
   File "notDriven.py", line 12, in TOP
     @always_comb
   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py",  
line 64, in always_comb
     c = _AlwaysComb(func, symdict)
   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py",  
line 203, in __init__
     raise AlwaysCombError(_error.EmptySensitivityList)
myhdl.AlwaysCombError: sensitivity list is empty
###########################################################

its because of this lines in the code
---------------------------
     sigTest=Signal(intbv(0)[4:])
     @always_comb
     def comb_setConst():
       sigTest.next=4
---------------------------
which in my understanding should be valid code




#################Case 2: (code)#################################
 from myhdl import *
 from random import randrange

ENUM_TYPE = enum('GIVE_ONE', 'GIVE_TWO')

def TOP(outvalue):
     sel_value=Signal(ENUM_TYPE.GIVE_TWO)

     #sel_value=Signal(intbv(0)[4:])

     @always_comb
     def combi_sel():
       if sel_value == ENUM_TYPE.GIVE_ONE :
	outvalue.next=1
       elif sel_value == ENUM_TYPE.GIVE_TWO :
	outvalue.next=2

     return instances()


def test_bench():
     outsignal=Signal(intbv(0)[4:])
     instanc_top=TOP(outsignal)

     interval = delay(10)
     @always(interval)
     def stimulus():
         print "Value of Output is", outsignal

     return  stimulus,instanc_top


if __name__ == '__main__':
     hello_inst = test_bench()

     sim = Simulation(hello_inst)
     print "-"*30 + "Simulation Started" + "-"*30
     sim.run(10)
     print "-"*30 + "Simulation Finished" + "-"*30


     outsignal=Signal(intbv(0)[4:])

     print "-"*30 + "Conversion To VHDL Started" + "-"*30
     toVHDL(TOP,outsignal)
#############################################################


#############Console Output:###############################
------------------------------Simulation  
Started------------------------------
Value of Output is 2
<class 'myhdl._SuspendSimulation'>: Simulated 10 timesteps
------------------------------Simulation  
Finished------------------------------
------------------------------Conversion To VHDL  
Started------------------------------
** ToVHDLWarning: Signal is not driven: sel_value
Traceback (most recent call last):
   File "Case2.py", line 45, in <module>
     toVHDL(TOP,outsignal)
   File  
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py", line  
165, in __call__
     _convertGens(genlist, siglist, vfile)
   File  
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py", line  
392, in _convertGens
     assert 0
AssertionError
####################################################


The Simulation runs but the conversion too vhdl or to Verilog aborts

if i dont use a ENUM   Signal for the "sel_value" the conversion works
so the unit changes to:
#############Case 2.5 (code)#################
def TOP(outvalue):
     #sel_value=Signal(ENUM_TYPE.GIVE_TWO)

     sel_value=Signal(intbv(0)[4:])

     @always_comb
     def combi_sel():
       if sel_value == ENUM_TYPE.GIVE_ONE :
	outvalue.next=1
       elif sel_value == ENUM_TYPE.GIVE_TWO :
	outvalue.next=2

     return instances()
######################################
then the simulation runs and the conversion works the only warning is
** ToVHDLWarning: Signal is not driven: sel_value
the resulting .vhd is not synthesisable because there is no "=" operator  
for enum type and unsingned