Re: [myhdl-list] Conversion error to vhdl

[Norbo <Nor...@gm...>]

On Wed, 23 Nov 2011 17:13:27 +0100, Christopher Felton  
<chr...@gm...> wrote:

> On 11/22/11 3:15 PM, Norbo wrote:
>> On Mon, 21 Nov 2011 17:28:05 +0100, Christopher Felton
>> <chr...@gm...>  wrote:
>>
>>> On 11/21/2011 8:52 AM, Oscar Diaz wrote:
>>>> 2011/11/19 Norbo<Nor...@gm...>:
>>>>> I have played a bit with myhdl and created the following:
>>>>>
>>>>> ----------------------------------------------------------
>>>>>    from myhdl import *
>>>>>
>>>>> def bin2gray(A,B, C, width):
>>>>>
>>>>>       """ Gray encoder.
>>>>>
>>>>>       B -- input intbv signal, binary encoded
>>>>>       G -- output intbv signal, gray encoded
>>>>>       width -- bit width
>>>>>
>>>>>       """
>>>>>       @always_comb
>>>>>       def logic():
>>>>>           C[0].next = A + B
>>>>
>>>> It seems that you have a bug here. Why you assign the result of a sum
>>>> to a single bit? that's the reason why the converter tried to use
>>>> "to_std_logic" for the output. If you want a normal sum, it should be
>>>>
>>>> C.next = A + B
>>>>
>>>> and the VHDL converter will put synthesizable code:
>>>>
>>>> C<= (A + B);
>>>>
>>>
>>> Good eye Oscar!
>>>
>>> Yes, there are a couple issues with the bin2gray that was provided (I
>>> assumed the bin2gray was an example for conversion means and not an
>>> actual bin2gray?).  I didn't notice at first glance but if you want to
>>> assign a single bit of a bit-vector you need to do:
>>>
>>>     C.next[0] = A + B
>>>
>>>
>>> If you assign the bit correctly the conversion works (even though it
>>> functional doesn't work).  Simulation will not work!.  Not sure why the
>>> converter didn't flag this?  Possible error detection enhancement.
>>>
>>> Also using the "+" operator instead of the bitwise "^" will cause
>>> problems in simulation.  The "+" will overflow the range for a single
>>> bit.
>>>
>>> My previous reply can be ignored and should be ignored.  If any changes
>>> need to be made they would be in the error catching/reporting and not
>>> modifications to the conversion.
>>>
>>> Regards,
>>> Chris
>>>
>>>> Or, if you want a binary to gray encoder, just use the example from
>>>> the documentation
>>>>
>>>> http://www.myhdl.org/doc/current/manual/conversion_examples.html#a-small-combinatorial-design
>>>>
>>>>
>>>> Best Regards
>>>>
>>
>> Well the thing is:
>>
>> If i write:
>>
>> C[4:0].next = A+B    in vhdl it gets ->   C(4-1 downto 0)<= resize(A +
>> B,4);
>>
>> or:
>>
>> C[1:0].next = A+B   in vhdl it gets ->   C(1-1 downto 0)<= resize(A +  
>> B,1);
>> which in  in my understanding this makes kind of sense because the  
>> result
>> is cropped to the output size. (maybe a warning would be nice, but it
>> could be difficult if the calculation gets longer)
>>
>>
>> but when i write :
>>
>> C[0].next = A+B
>> (which is actually the same as the above C[1:0].next = A+B)
>>       in vhdl it gets ->   C(0)<= to_std_logic(A + B);
>> and is not synthesisable.
>>
>>
>
> As mentioned, the above is the incorrect syntax.  The converted results
> are unreliable.  To do bit indexing you need to do:
>
>    C.next[0] = A[0] + B[1]
>
> If you do C[0].next that is used for a list of signals.  If you run a
> simulation (testbench) this error will be identified.
>
> Review the following links:
> http://www.myhdl.org/doc/current/manual/intro.html#bit-indexing
> http://www.myhdl.org/doc/current/manual/conversion_examples.html#a-small-combinatorial-design
>
> Also, run a simple simulation.  That will give you some more insight
> into the issue.
>
> Regards,
> Chris

Sorry that i keep bagging, i really like myhdl and i really want to get it  
better
so if i write:

C.next[0] = A[0] + B[1]

the line which is produced is:

C(0) <= to_std_logic(to_unsigned(A(0), 1) + to_unsigned(B(0), 1));

and it is not synthesisable because of the to_std_logic.


wheras:
C.next[1:0] = A[0] + B[1]

gets:
C(1-1 downto 0) <= (to_unsigned(A(0), 1) + to_unsigned(B(1), 1));
and is synthesisable.


thanks in advance