Re: [myhdl-list] Signal has multiple drivers

[Christopher F. <chr...@gm...>]

On 11/22/11 6:29 PM, garyr wrote:
> Code that appears to be OK when simulated produces errors "Signal has
> multiple drivers" when I attempt to convert it to Verilog. In my case the
> two drivers never access the signal at the same time so there should be no
> problem. Google didn't turn up any useful information.
>
> In one case a rather simple change eliminated the problem. Another
> occurrence I eliminated by adding a multiplexer that routed a start and an
> 8-bit command signal to the shared module. A third occurrence involves an
> unsigned division module having 32-bit parameters dividend, divisor and
> quotient. The dividend and divisor signals would have multiple drivers.
> Using a multiplexer approach here would be very costly in terms of bits. Is
> there some other way of dealing with this problem? Couldn't MyHDL just issue
> a warning?
>
>

You can not have multiple drivers if you wish to have a physical 
realization of the circuit.  The circuits are always driving their 
outputs, in the physical circuit -without including tri-states, mux, 
etc- there isn't the notion of not driving an output.  Depending on the 
type of source and sinks in the technology you could implement "wire 
and" and "wire or" but I am unaware of any tools (synthesis, par) that 
will support multiple drivers.

If you wish to have a physical realization of your circuit description 
you will need to define how the outputs are arbitrated.  This could be 
as simple as "or"ing the outputs together but it depends on your circuit.

Simulation allows multiple drivers so you can easily do things in 
testbenches, portions of the HDL that are not intended to be 
synthesized.  This is is the same in Verilog and VHDL.  Multiple drivers 
are not part of the synthesizable subset.  Even if MyHDL were to let 
this pass you would fail when you try and synthesize the underlying HDL.

Hope that helps,
Chris