[myhdl-list] Signal has multiple drivers

[garyr <ga...@fi...>]

Code that appears to be OK when simulated produces errors "Signal has
multiple drivers" when I attempt to convert it to Verilog. In my case the
two drivers never access the signal at the same time so there should be no
problem. Google didn't turn up any useful information.

In one case a rather simple change eliminated the problem. Another
occurrence I eliminated by adding a multiplexer that routed a start and an
8-bit command signal to the shared module. A third occurrence involves an
unsigned division module having 32-bit parameters dividend, divisor and
quotient. The dividend and divisor signals would have multiple drivers.
Using a multiplexer approach here would be very costly in terms of bits. Is
there some other way of dealing with this problem? Couldn't MyHDL just issue
a warning?