Re: [myhdl-list] Third-party modules?

[Christopher F. <chr...@gm...>]

On 11/20/2011 11:43 AM, garyr wrote:
> ----- Original Message -----
> From: "Christopher Felton"<chr...@gm...>
> To:<myh...@li...>
> Sent: Saturday, November 19, 2011 8:50 PM
> Subject: Re: [myhdl-list] Third-party modules?
>
>
>> On 11/19/11 8:41 PM, garyr wrote:
>>> Thanks for the information. Can this type of code be tested with the
>>> MyHDL
>>> simulator? I have tried something very similar to that but it appeared to
>>> have no effect during simulation.
>>
>> If you do CoSimulation you can test the 3rd party IP (presumed to be
>> Verilog or VHDL).  If you want to do MyHDL simulation only, you have to
>> create a model for the IP (or better yet request the IP vendor to create
>> a MyHDL/Python model :) ).
>>
>> Hope that helps,
>> Chris
>
> I should have described my problem in more detail. I'm not actually dealing
> with a third-party module, just modules I have written. I have a utility
> module that I wish to use (not concurrently) with two other modules . I
> wrote some test code and followed the procedure described in Section 8.8
> of the MyHDL manual (which you also described) and inserted a bit of Verilog
> code in the primary module that I thought would instantiate the utility
> module. But when I run the simulation it appears that the utility module is
> not instantiated. Here is a bit of my test code:
>
> def test(overflow, count):
>     @always(overflow.negedge)
>     def logic():
>         pass
>   count.driven = "wire"
>   return logic
> test.verilog_code =\
> """overflowCounter inst_1(.ovfl($overflow), .overflowCount($count));"""
>
> def simpleCounter(reset, signal, gate, count, ofCount):
>     overflow = Signal(intbv(0)[5:])
>     instTest = test(overflow, ofCount)
>     instCounter = counter(reset, signal, gate, count, overflow)
>   return instTest, instCounter
>
> The module counter (not shown) is a gated counter; the signal overflow is
> toggled when the counter overflows. The function of the module
> overflowCounter (also not shown) is to count the number of times overflow
> occurred. These two modules when instantiated together as in section 8.4 of
> the manual or in a test bench function correctly. I know very little about
> HDL so the bit of Verilog code above may be incorrect - please comment on
> that. Assuming the Verilog code is correct, if I instantiate the module
> simpleCounter in a test bench will all of the code, overflowCounter
> included, be simulated?
>
> Many thanks,
> Gary Richardson


If you simply want to test Verilog/VHDL code with MyHDL the above 
(previous reply) might not be the approach you want.

You should look at the cosimulation sections of the manual if you simply 
want to test Verilog modules.

The previous response would be for mixing MyHDL/Verilog for the final 
HDL that will be synthesized.  The above is like a "black box" 
definition.  Where the logic will be filled in at some later period.

Regards,
Chris

>
>>
>>>
>>> ----- Original Message -----
>>> From: "Christopher Felton"<chr...@gm...>
>>> To:<myh...@li...>
>>> Sent: Saturday, November 19, 2011 3:00 PM
>>> Subject: Re: [myhdl-list] Third-party modules?
>>>
>>>
>>>> On 11/19/11 12:57 PM, garyr wrote:
>>>>> One of the entries in the MyHDL Frequently Asked Questions states that
>>>>> third-party modules may be instantiated by using "user-defined code to
>>>>> replace a MyHDL module by a corresponding instantiation".  My attempts
>>>>> at this have not been successful. Could someone point me to an example?
>>>>>
>>>>> Thanks in advance for your replies.
>>>>>
>>>>>
>>>>
>>>> Here is a reply from a earlier, similar, inquiry.  You might want to
>>>> refer to the old thread, http://bit.ly/uHcVZi.
>>>>
>>>> Regards,
>>>> Chris
>>>>
>>>>> Here is a small example to achieve what (I think) you are describing.
>>>>> More information can be found here,
>>>>> http://www.myhdl.org/doc/current/manual/conversion_examples.html#conv-usage-custom
>>>>>
>>>>> from myhdl import *
>>>>>
>>>>> def BurriedInstance(clk, rst, data_in, data_out):
>>>>>
>>>>>        # ... Some Code
>>>>>        bi = nativeInstance(clk, rst, data_in, data_out)
>>>>>        # ... Some More Code
>>>>>
>>>>>        return bi  #other generators
>>>>>
>>>>> def nativeInstance(clk, rst, data_in, data_out):
>>>>>
>>>>>        @always(clk, rst, data_in)
>>>>>        def pass_thru():
>>>>>            pass
>>>>>        data_out.driven = "wire"
>>>>>
>>>>>        nativeInstance.vhdl_code = """
>>>>>        P1:ppc port map($clk, $rst, $data_in, $data_out);
>>>>>        """
>>>>>
>>>>>        return pass_thru
>>>>>
>>>>>
>>>>> if __name__ == '__main__':
>>>>>        clk = Signal(False)
>>>>>        rst = Signal(False)
>>>>>        data_in  = Signal(intbv(0)[8:])
>>>>>        data_out = Signal(intbv(0)[8:])
>>>>>        toVHDL(BurriedInstance, clk, rst, data_in, data_out)
>>>>>
>>>>>
>>>>
>>>>
>>>>