Re: [myhdl-list] Conversion error to vhdl

[Oscar D. <osc...@gm...>]

2011/11/19 Norbo <Nor...@gm...>:
> I have played a bit with myhdl and created the following:
>
> ----------------------------------------------------------
>  from myhdl import *
>
> def bin2gray(A,B, C, width):
>
>     """ Gray encoder.
>
>     B -- input intbv signal, binary encoded
>     G -- output intbv signal, gray encoded
>     width -- bit width
>
>     """
>     @always_comb
>     def logic():
>         C[0].next = A + B

It seems that you have a bug here. Why you assign the result of a sum
to a single bit? that's the reason why the converter tried to use
"to_std_logic" for the output. If you want a normal sum, it should be

C.next = A + B

and the VHDL converter will put synthesizable code:

C <= (A + B);

Or, if you want a binary to gray encoder, just use the example from
the documentation

http://www.myhdl.org/doc/current/manual/conversion_examples.html#a-small-combinatorial-design


Best Regards

-- 
Oscar Díaz
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