Re: [myhdl-list] Conversion error to vhdl

[Norbo <Nor...@gm...>]

On Sun, 20 Nov 2011 15:37:29 +0100, Christopher Felton  
<chr...@gm...> wrote:

> On 11/19/11 4:22 PM, Norbo wrote:
>> I have played a bit with myhdl and created the following:
> [snip]
>> --------------------------------------------------
>> -- File: bin2gray.vhd
>> -- Generated by MyHDL 0.7
>> -- Date: Sat Nov 19 22:54:16 2011
>>
>>
>> library IEEE;
>> use IEEE.std_logic_1164.all;
>> use IEEE.numeric_std.all;
>> use std.textio.all;
>>
>> use work.pck_myhdl_07.all;
>>
>> entity bin2gray is
>>       port (
>>           A: in unsigned(7 downto 0);
>>           B: in unsigned(7 downto 0);
>>           C: out unsigned(7 downto 0)
>>       );
>> end entity bin2gray;
>> -- Gray encoder.
>
> If you notice the generated VHDL uses a library, pck_myhdl_07.  This is
> an additional VHDL file that is generated with the conversion.  You need
> to include this file (pck_myhdl07.vhd) in your synthesis tools.
>
> If it looks like the file did not generate correctly, delete the
> pck_myhdl_07 and rerun the conversion.  If you have to do this let use  
> know.
>
> Hope that helps,
> Chris
>
>


I deleted the file  (pck_myhdl07.vhd) and it  successfully regenerated,  
after including this file
in the synthesis tool (lattice diamond) i had the same error (No matching  
overload for to_std_logic). There seems to be no function to_std_logic in  
the (pck_myhdl07.vhd).
The only "to_std_logic" functions in the generated pck_myhdl07.vhd pack  
are:

     function to_std_logic (arg: boolean) return std_logic;

     function to_std_logic (arg: integer) return std_logic;

an version which takes an unsigned is missing. I also couldn't find such  
an version of the "to_std_logic" function in the ieee library s

greetings,
Norbert