Re: [myhdl-list] Conversion error to vhdl

[Christopher F. <chr...@gm...>]

On 11/19/11 4:22 PM, Norbo wrote:
> I have played a bit with myhdl and created the following:
[snip]
> --------------------------------------------------
> -- File: bin2gray.vhd
> -- Generated by MyHDL 0.7
> -- Date: Sat Nov 19 22:54:16 2011
>
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> use std.textio.all;
>
> use work.pck_myhdl_07.all;
>
> entity bin2gray is
>       port (
>           A: in unsigned(7 downto 0);
>           B: in unsigned(7 downto 0);
>           C: out unsigned(7 downto 0)
>       );
> end entity bin2gray;
> -- Gray encoder.

If you notice the generated VHDL uses a library, pck_myhdl_07.  This is 
an additional VHDL file that is generated with the conversion.  You need 
to include this file (pck_myhdl07.vhd) in your synthesis tools.

If it looks like the file did not generate correctly, delete the 
pck_myhdl_07 and rerun the conversion.  If you have to do this let use know.

Hope that helps,
Chris