[myhdl-list] Conversion error to vhdl

[Norbo <Nor...@gm...>]

I have played a bit with myhdl and created the following:

----------------------------------------------------------
 from myhdl import *

def bin2gray(A,B, C, width):

     """ Gray encoder.

     B -- input intbv signal, binary encoded
     G -- output intbv signal, gray encoded
     width -- bit width

     """
     @always_comb
     def logic():
         C[0].next = A + B
		
     return logic


def main():
     width = 8

     A = Signal(intbv(0)[width:])
     B = Signal(intbv(0)[width:])
     C = Signal(intbv(0)[width:])
	
     toVHDL(bin2gray, A, B,C, width)

if __name__ == '__main__':
     main()
---------------------------------------------


after conversion it gives me the following .vhd file:

--------------------------------------------------
-- File: bin2gray.vhd
-- Generated by MyHDL 0.7
-- Date: Sat Nov 19 22:54:16 2011


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_07.all;

entity bin2gray is
     port (
         A: in unsigned(7 downto 0);
         B: in unsigned(7 downto 0);
         C: out unsigned(7 downto 0)
     );
end entity bin2gray;
-- Gray encoder.
-- 
-- B -- input intbv signal, binary encoded
-- G -- output intbv signal, gray encoded
-- width -- bit width

architecture MyHDL of bin2gray is


begin





C(0) <= to_std_logic(A + B);

end architecture MyHDL;
--------------------------------------

this seems not to be synthesisable because there is no "to_std_logic"  
function for unsigned type
do i miss something?