[myhdl-list] State machine modeling

[Oscar D. <osc...@gm...>]

Hi

Recently I had some problems converting state machines to VHDL. In my
models I use two generators: one with the state sequence and another
with the output based on the states. For this second generator I use
@always_comb, since its just combinatorial logic. Works perfect in
simulation but fails on conversion. Then I did a workaround: put
manually a sensitivity list with @always(list_of_signals) and then the
conversion step worked fine.

I wonder if it's a bug in conversion, or if there's a better way to
model a state machine. I attach a small example to show my dilemma.

Best regards

-- 
Oscar Díaz
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