[myhdl-list] Pythonic Test frameworks

[Christopher F. <chr...@gm...>]

Looking for some opinions on methods to make my testbenches more 
Pythonic.  I have been humbled more often than not with my Python 
programming skills, or lack there of (http://bit.ly/uQeRGm).  And my 
testbenches seem to be old-school version of my Verilog/VHDL equivalent 
testbences.  Looking to move from a testbench to a test framework.

Frequently I will create a single testbench and have a bunch of 
testcases in the testbench.  In some cases I will create multiple 
(different) forms in test_ functions to use with py.test.

But too often, majority of my test cases are in this single testbench. 
What I would like to do is leverage the py.test framework but only 
define connections, models, etc *once*.  Using the USB interface project 
(USBP, http://bit.ly/sPEMC1) as an example I used something like the 
following.

~~~ [Example Code] ~~~
class BaseSim()

    def __init__(self, ...):
       # all top-level signal definitions, dut instance and interface
       # model instances
       ...

   def GetGens():
       # return all the generators for

def test_case1():
    bs = BaseSim()

    @instance
    def tb_stimulus():
       yield bs.WriteRegister(0x00, 42)
       rval = [0]
       yield bs.ReadRegister(0x00, val)
       assert rval[0] == 42
       raise StopSimulation

    Simulation((tb_stimulus, bs.GetGens())).run()

def test_case2():
    bs = BaseSim()

    @instance
    def tb_stimulus
       bs.someSignal.next = True
       yield delay(3)
       bs.someSignal.next = False
       # check some condition
       raise StopSimulation

   Simulation((tb_stimulus, bs.GetGens())).run()

~~~ [End Example Code]~~~

Other methods that are more flexible?  Is it worth it to add the 
instantiations and connection signals to a class or just in a module?

Thanks in advance,
Chris