[myhdl-list] Problems with MyHDL and Modelsim cosimulation

[David G. <dsg...@gm...>]

I'm trying to get the basic cosimulation tests to pass with modelsim,
but they're currently failing. I built the VPI with the following
Makefile fragment:

myhdl.vpi: myhdl.c myhdl_table.c
        gcc -c -g -fPIC -I ${MODELSIM_INC} myhdl.c myhdl_table.c
        ld -shared -E -o myhdl_vpi.so myhdl.o myhdl_table.o

Modelsim seems to like myhdl_vpi.so (so far so good).

Next, I modified dff.py to use the following commands:

cmd = "vlog ../../test/verilog/dff.v ../../test/verilog/dut_dff.v"
def dff(q, d, clk, reset):
  os.system(cmd)
  return Cosimulation("vsim -c -pli myhdl_vpi.so dff -do sim.do", **locals())

and the contents of sim.do are:

run -all
quit -f

I get "Premature simulation end" errors (line 88 in _Cosimulation.py,
MyHDL 0.7) for all the tests.

Does anyone have experience getting MyHDL and Modelsim to play nicely?

Thanks,
David