Re: [myhdl-list] my patches

[Sébastien B. <seb...@mi...>]

On 10/21/2011 12:13 PM, Jan Decaluwe wrote:
> In that case, how should the Signals in question be initialized?
> Remember, the initial value is an explicit part of the Signal
> construction, you have to choose one. (This is MyHDL, not Verilog).
> It certainly would seem confusing and dubious coding if the
> initial value would be different from the "constant driver"
> value. Any code reviewer would spot this as an obvious weak point
> in the code, and suggest to initialize the Signal to the
> "constant" value.

This does not shock me more than the signal having a different value 
than its initial one after it has been driven by, say, a AND gate.

In my opinion, directly supporting constant logic functions is more 
practical (e.g. with less typing for the user) and cleaner design than 
having to work around the MyHDL limitation by declaring a new signal 
with the constant value you need, and connecting it to the signal you 
want to drive.

Maybe the initial values could be made optional? And give an error if 
any signal without an initial value is not driven?

S.