[myhdl-list] MyHDL Success Stories

[Christopher F. <chr...@gm...>]

On 10/6/2011 12:14 PM, Jan Decaluwe wrote:
> On 10/06/2011 12:35 AM, Christopher Felton wrote:
>
>> I will see if I can provide some details on the MyHDL designs I have
>> fielded.  If not I will provide some generic descriptions in the
>> user/project space.
>
> Great, thanks. Once we have 4-5 projects, I propose to
> add a "Silicon Success" page with the links, on a prominent
> position on the website.
>
>

The following are commercial projects which I have used MyHDL.

1.  [FPGA] High-speed satellite communication link, NASA's TDRSS.  The 
modem was developed for the NASA's TKUP project while I was at RTLogic. 
  MyHDL was used for modeling and verification of high-speed DSP blocks.
http://www.rtlogic.com/press_releases/TKUP_Press_Release_8.31.07.pdf.

2.  [FPGA] Custom proprietary modem used over a non-common medium. 
MyHDL was used for modeling, verification, and implementation of a 
couple IP blocks.  This project is currently deployed in small numbers.

3.  [FPGA] MyHDL is used by DSPtronics.  These were small examples 
similar to the wiki space.  The platform was used by students at the 
University of Colorado, Colorado Springs (UCCS), 
http://www.eas.uccs.edu/wickert/ece4890/lecture_notes/ece4890_RFPs_Fa2011.pdf 
(note the overused graphic :) ).  I am not geographically located near 
this anymore (haven't been for 3 years), I am a little out of the loop. 
  I don't know how much has actually been done by the students (if any 
at all).  I don't know if this qualifies as a success story.

4.  [ASIC] Latest project, MyHDL was used for all verification of a 
digital subsystem in a mixed-signal IC.  The die have been received and 
are in the process of hardware testing.  I will be able to share more on 
this development in a couple months (maybe 6mos or more) after the 
research announcements/publications have been released.  In addition 
MyHDL was used completely to develop all logic for test/interface FPGA.

 From my perspective, MyHDL saved effort in developing and verifying 
these projects.  In the latest projects, kinda fallen into a nice flow, 
where:

   Tests and Test Infrastructure developed
   ASIC logic developed
   ASIC logic verified with test environment
     (post-syn and post-layout cosims)
   Final HW test fixture development
     FPGA logic, verified with previous test and design
   ASIC logic prototyped of FPGA (early FPGA proto to FW devs)
   Test fixture and prototype FPGA tested together
   Final hardware interface/tested with test-fixture

I liked this flow because it had multiple items cross checking each 
other as well as reuse.  The simulation test environment and FPGA test 
fixture are able to use the same Python test code.  As test code evolved 
it could be run against HDL simulations, FPGA prototype, and eventually 
final hardware.

Regards,
Chris