Re: [myhdl-list] CHIP, a myhdl like project

[Jan D. <ja...@ja...>]

On 10/17/2011 10:38 AM, Sébastien Bourdeauducq wrote:
> On 10/17/2011 09:51 AM, Jan Decaluwe wrote:
>> One way, and the big winner to date, is the event-driven paradigm.
>> That is what VHDL, Verilog and MyHDL have in common.
>>
>> It is incorrect (although often done) to call such languages "RTL"
>> languages. Instead, RTL is a semantic subset of such languages.
>> There are other ways to do RTL, but I'm convinced that this is the
>> single way to do it right.
>
> Oh, come on. For synchronous systems, which is what the common
> mortals who design with FPGAs almost always deal with, the
> event-driven paradigm is just a complicated way of getting things
> done. Cycle-based simulations are simpler, faster, and also correct.

I was not talking about simulation techniques, but about the
fundamental paradigm behind language design. Verilator is still
a Verilog simulator, and Verilog is an event-driven language.

Historically, the name RTL (Register Transfer Language) refers
to a totally different paradigm: one in which registers are explicit
and (clock) events are implicit. AHDL is probably the best example
that is still in use. Many other RTL languages of this type
have been proposed over the years. They are all but forgotten, to
the point that it is even hard find any traces about them on
the internet. And of course, this gives room to the occasional
genius to construct a new "fully synthesizable" HDL that is
"much less verbose" than Verilog or VHDL.

In event-driven RTL, (clock) events are explicit and registers are
implicit (inferred). We kept the name RTL, but that really is a
misnomer. Something like "clocked behavior language" would be
more accurate. Regardless of the name, this is the winning
paradigm for RTL. And the reason it has won is that many
designers need much more powerful modeling than just RTL,
within the same language.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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