Re: [myhdl-list] toVHDL Observation

[Sébastien B. <seb...@mi...>]

On 10/17/2011 10:25 AM, Jan Decaluwe wrote:
> The mechanisms in the convertor to avoid name and keyword clashes
> are broken (in the sense that they aren't present :-)).
>
> I keep delaying it, because the problem is not that simple in
> general.

How about using extended names (at least for internal signals)?

Verilog:
http://eesun.free.fr/DOC/VERILOG/verilog_manual1.html "Escaped 
Identifiers (identifier whose first character is a backslash (\))permit 
non alphanumeric characters in Verilog name. The escaped name includes 
all the characters following the backslash until the first whitespace 
character."

VHDL:
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html "there are a set 
of extended identifier rules which allow identifiers with any sequence 
of characters. ..."