Re: [myhdl-list] CHIP, a myhdl like project

[Sébastien B. <seb...@mi...>]

On 10/17/2011 09:51 AM, Jan Decaluwe wrote:
 > One way, and the big winner
 > to date, is the event-driven paradigm. That is what
 > VHDL, Verilog and MyHDL have in common.
 >
 > It is incorrect (although often done) to call such
 > languages "RTL" languages. Instead, RTL is
 > a semantic subset of such languages. There are
 > other ways to do RTL, but I'm convinced that this
 > is the single way to do it right.

Oh, come on. For synchronous systems, which is what the common mortals 
who design with FPGAs almost always deal with, the event-driven paradigm 
is just a complicated way of getting things done. Cycle-based 
simulations are simpler, faster, and also correct.

> The back-end is VHDL RTL, and
> as I noticed before, I think MyHDL would have been a
> better choice.

Then maybe you'll like my HLS prototype better? If so, please consider 
merging my patches which are needed to support it.

 > * "A hardware model written in an imperative style cannot be
 > synthesised"
 >
 > This is wrong: an imperative style is actually very useful to describe
 > combinatorial and clocked RTL logic.
 > (...)
 > I agreed with the author that RTL is "low-level". However, it  is
 > definitely not as "low-level" as he suggests. If the starting
 > point is shaky, I don't have a lot of confidence in the "solution".

I think he meant "imperative style for a complete algorithm", not 
"imperative style for describing what can be done within one clock 
cycle". From this point of view, it is true that the efficient synthesis 
of a complex algorithm written in imperative style is a very difficult 
problem, and that using a different "dataflow" paradigm can make sense.

S.