[myhdl-list] toVHDL Observation

[Christopher F. <chr...@gm...>]

Not much thought or investigation behind this.  But I notice today when 
converting a state-machine which used enum() for state definitions to 
VHDL, that I had to be careful with the names I chose.  VHDL keywords 
and other VHDL naming rules had to be considered (obeyed).

I had a state-machine I intended to convert to Verilog and VHDL but had 
only converted to Verilog.  When I tried VHDL, D'oh.  Simply, had to 
rename some of the states, like 'WAIT' and 'END' as well as removing 
trailing underscores (which were place-holders).

Regards,
Chris