Re: [myhdl-list] howto cite MyHDL

[Christopher F. <chr...@gm...>]

On 10/5/11 9:58 AM, Jan Decaluwe wrote:
> On 10/05/2011 12:21 PM, Christopher Felton wrote:
>> On 10/2/11 9:33 PM, Dan White wrote:
>>> I've used MyHDL for some digital parts on my last mixed-signal ASIC
>>> for my PhD research.  The chip is currently in fab and I've been
>>> waiting to get a die photo after testing to announce here the second
>>> verified silicon using MyHDL in the flow.
>>>
>>
>> Congratulations as well!  It seems MyHDL might have found a niche in
>> mixed-signals ICs.
>
>    From what I see, this is becoming the niche of ASICs tout court:
> pure digital designs are systematically migrating to FPGAs,
> the few exceptions being super high volume and complexity designs.
>
True, very true, I agree.

> Therefore - there must be some MyHDL FPGA success stories
> out there as well. We may not have heard about them because
> the typical ASIC milestones like sign-off and tape-out are
> not applicable (fortunately I would add.) But I would encourage
> anyone with such success stories (especially FPGAs in production)
> to tell us about it if possible.
>
I will see if I can provide some details on the MyHDL designs I have 
fielded.  If not I will provide some generic descriptions in the 
user/project space.

> More than anything else, I think the project needs the
> credibility from working silicon, FPGAs included.
>