[myhdl-list] Sigma-Delta DAC

[Bob C. <Fl...@gm...>]

I'm trying to learn from this code: http://www.myhdl.org/doku.php/projects:dsx1000

I first ran dac_dsx1000_ut.py, and all tests passed.  I next tried to run dac_dsx1000_syn.py, but got the following errors:

    $ pypy ./dac_dsx1000_syn.py
    CLK_HZ =  16000000
    OUTPUT_FREQ_HZ =  440
    FVAL =  461
    Traceback (most recent call last):
       File "app_main.py", line 53, in run_toplevel
       File "./dac_dsx1000_syn.py", line 137, in<module>
         toVerilog(top, clk, rst, pdm_o, CLK_HZ)
       File "/usr/lib/pypy-1.6/site-packages/myhdl/conversion/_toVerilog.py", line 128, in __call__
         h = _HierExtr(name, func, *args, **kwargs)
       File "/usr/lib/pypy-1.6/site-packages/myhdl/_extractHierarchy.py", line 228, in __init__
         _top = dut(*args, **kwargs)
       File "./dac_dsx1000_syn.py", line 97, in top
         @always_comb
       File "/usr/lib/pypy-1.6/site-packages/myhdl/_always_comb.py", line 64, in always_comb
         c = _AlwaysComb(func, symdict)
       File "/usr/lib/pypy-1.6/site-packages/myhdl/_always_comb.py", line 203, in __init__
         raise AlwaysCombError(_error.EmptySensitivityList)
    AlwaysCombError: sensitivity list is empty


I got the same errors when using python instead of pypy.

My naive solution was to modify dac_dsx1000_syn.py to add 'rst' to top()'s parameter list, move the rst declaration to line 132, and comment-out the definition of rstDrv(), after which the above errors went away.

While the tests in dac_dsx1000_ut.py still pass, I'm now torturing my newbie brain to figure out how best to update the testbench to include testing of rst.  The pain is terrible, but slow progress is being made.

I haven't yet fed the generated Verilog code to ISE, nor have I run a cosimulation to test it.

Questions:
1. Is this the right approach to use to fix this problem?
2. When the fix is complete and tested, where should the updated code go?

TIA,

-BobC